RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters

High-Performance Computing (HPC) have evolved to be used to perform simulations of systems where physical experimentation is prohibitively impractical, expensive, or dangerous. This paper provides a general overview and showcases the analysis of non-functional properties in RISC-V-based platforms for HPCs. In particular, our analyses target the evaluation of power and energy control, thermal management, and reliability assessment of promising systems, structures, and technologies devised for current and future generation of HPC machines. The main set of design methodologies and technologies developed within the activities of the Future and HPC & Big Data spoke of the National Centre of HPC, Big Data and Quantum Computing project are described along with the description of the testbed for experimenting two-phase cooling approaches

First wave of COVID-19 in Venezuela:Epidemiological, clinical, and paraclinical characteristics of first cases

The coronavirus disease 2019 (COVID-19) pandemic has particularly affected countries with weakened health services in Latin America, where proper patient management could be a critical step to address the epidemic. In this study, we aimed to characterize and identify which epidemiological, clinical, and paraclinical risk factors defined COVID-19 infection from the first confirmed cases through the first epidemic wave in Venezuela. A retrospective analysis of consecutive suspected cases of COVID-19 admitted to a sentinel hospital was carried out, including 576 patient cases subsequently confirmed for severe acute respiratory syndrome coronavirus 2 infection. Of these, 162 (28.1%) patients met the definition criteria for severe/critical disease, and 414 (71.2%) were classified as mild/moderate disease. The mean age was 47 (SD 16) years, the majority of which were men (59.5%), and the most frequent comorbidity was arterial hypertension (23.3%). The most common symptoms included fever (88.7%), headache (65.6%), and dry cough (63.9%). Severe/critical disease affected mostly older males with low schooling (p < 0.001). Similarly, higher levels of glycemia, urea, aminotransferases, total bilirubin, lactate dehydrogenase, and erythrocyte sedimentation rate were observed in severe/critical disease patients compared to those with mild/moderate disease. Overall mortality was 7.6% (44/576), with 41.7% (28/68) dying in hospital. We identified risk factors related to COVID-19 infection, which could help healthcare providers take appropriate measures and prevent severe clinical outcomes. Our results suggest that the mortality registered by this disease in Venezuela during the first epidemic wave was underestimated. An increase in fatalities is expected to occur in the coming months unless measures that are more effective are implemented to mitigate the epidemic while the vaccination process is ongoing

Secure communication protocol for wireless sensor networks

We propose a new communication protocol for wireless sensor networks, allowing to make them secure with respect to malicious attacks. Compared to standard secure protocols (e.g., the IEEE 802.15.4 and the ZigBee), the one we propose allows to increase security significantly, at negligible impact on node complexity. A possible hardware scheme to implement our protocol is also proposed

Novel approach to reduce power droop during scan-based logic BIST

Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss. Several solutions have been proposed in the literature to reduce the PD during test of combinational ICs, while fewer approaches exist for sequential ICs. In this paper, we propose a novel approach to reduce peak power/power droop during test of sequential circuits with scan-based Logic GIST. In particular, our approach reduces the switching activity of the scan chains between following capture cycles. This is achieved by an original generation and arrangement of test vectors. The proposed approach presents a very low impact on fault coverage and test time, while requiring a very low cost in terms of area overhead